1. Field
The present invention relates to a phase locked loop system having locking and tracking modes of operation.
2. Background
Today, virtually every wireless device, such as cell phones, wireless laptops, personal digital assistants having wireless capabilities, WiFi networking equipment, etc., contains one or more phase locked loop (PLL) circuits. Basically, a PLL circuit is used to synthesize or otherwise generate precise, stable high frequency signals. Typically, in a PLL circuit, a reference signal is input to a phase detector or a phase-frequency detector. The phase detector compares the input reference signal to the output signal from a voltage controlled oscillator (VCO). The difference in the phase between these two signals is determined and the resultant difference signal is then processed by a loop filter. The function of the loop filter is to stabilize the loop and to filter out unwanted noise in the system. The filtered signal is input to control the operation of the VCO. In turn, the output from the VCO is fedback as an input to the phase detector via an integer divider, fractional divider, or a mixer. This feedback loop acts to servo the output from the VCO to that of the reference signal. By itself, the VCO is unstable and tends to drift in terms of frequency and phase, which is highly undesirable and problematic. However, by feeding back the VCO output signal and essentially enslaving the VCO to the reference signal, a more stable and precise output signal is thereby achieved.
Due to their unique ability to generate precise and yet stable high frequency signals, PLL circuits are found in a wide variety of applications ranging from modulators and demodulators to encoders and decoders, as well as controllers and other circuitry which make use of such high frequency signals. In the case of modulators, one common application of a PLL circuit entails applying phase modulation to a carrier signal. The phase modulated carrier signal is then processed and transmitted over-the-air as a radio frequency (RF) signal. Typically, the baseband I and Q signals containing speech and/or data information, are converted into an intermediate frequency (IF) signal by a phase quadrature modulator. This IF signal is then input to the PLL circuit as the reference signal. Initially, the PLL circuit locks onto the reference IF signal, and later it subsequently tracks the phase of the reference IF signal. In this manner, the high frequency signal output from the PLL circuit is essentially enslaved to the phase of the information carrying IF signal. Consequently, the PLL circuit performs the critical functions of upconverting the IF signal to the higher frequency of the carrier signal, while at the same time, locking onto and tracking the phase of the reference IF signal from the phase quadrature modulator.
Ideally, the PLL circuit would have the ability to instantaneously lock onto and then precisely track the phase of the reference IF signal. Unfortunately, these two goals are conflicting due to the physics underlying filter designs when applied to the loop filter of a PLL circuit. One type of PLL design, commonly referred to as a Type 2 PLL, enables the DC operating point of the VCO to be set over a wide range of voltages. This is advantageous because it directly translates into superior locking performance. However, a Type 2 PLL exhibits poor group delay. The group delay defines the phase characteristics across the frequencies of interest. The deviation in the group delay inherent to Type 2 PLLs causes the phase of the VCO to deviate from that of the reference IF signal. Hence, the Type 2 PLL is not well suited for tracking the IF signal, once lock has been established.
Another type of PLL design, commonly referred to as a Type 1 PLL, has a group delay which is more constant as compared to those of the Type 2 PLL. This characteristic makes the Type 1 PLL superior at tracking the reference IF signal. However, the disadvantage to using a Type 1 PLL is that it becomes harder to set the correct DC operating voltage to the VCO. Initially, the reference IF signal will start off at one phase frequency, whereas the VCO signal has some different, arbitrary phase frequency. The phase of the VCO signal must be made to match, or lock onto, the phase of the reference IF signal. If initially, the phases frequencies of these two signals are far apart, it may be impossible, difficult, or time consuming for a Type 1 PLL to eventually force the phase (and therefore frequency) of the VCO signal to match that of the reference IF signal.
Thus, PLL circuit designers are faced with a dilemma. On the one hand, a PLL circuit can be designed by implementing a Type 1 PLL. The advantage of implementing a Type 1 PLL is its superior tracking performance. The disadvantage is that a Type 1 PLL suffers from degraded locking functionality. On the other hand, a PLL circuit can be designed by implementing a Type 2 PLL. The Type 2 PLL enables the PLL circuit to better lock onto a reference IF signal. However, the downside to using a Type 2 PLL is the fact that it is not the most qualified filter for tracking the reference IF signal.